Silicon Labs /Series1 /EFM32GG11B /EFM32GG11B840F1024IQ100 /PRS /ROUTEPEN

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ROUTEPEN

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH0PEN)CH0PEN 0 (CH1PEN)CH1PEN 0 (CH2PEN)CH2PEN 0 (CH3PEN)CH3PEN 0 (CH4PEN)CH4PEN 0 (CH5PEN)CH5PEN 0 (CH6PEN)CH6PEN 0 (CH7PEN)CH7PEN 0 (CH8PEN)CH8PEN 0 (CH9PEN)CH9PEN 0 (CH10PEN)CH10PEN 0 (CH11PEN)CH11PEN 0 (CH12PEN)CH12PEN 0 (CH13PEN)CH13PEN 0 (CH14PEN)CH14PEN 0 (CH15PEN)CH15PEN 0 (CH16PEN)CH16PEN 0 (CH17PEN)CH17PEN 0 (CH18PEN)CH18PEN 0 (CH19PEN)CH19PEN 0 (CH20PEN)CH20PEN 0 (CH21PEN)CH21PEN 0 (CH22PEN)CH22PEN 0 (CH23PEN)CH23PEN

Description

I/O Routing Pin Enable Register

Fields

CH0PEN

CH0 Pin Enable

CH1PEN

CH1 Pin Enable

CH2PEN

CH2 Pin Enable

CH3PEN

CH3 Pin Enable

CH4PEN

CH4 Pin Enable

CH5PEN

CH5 Pin Enable

CH6PEN

CH6 Pin Enable

CH7PEN

CH7 Pin Enable

CH8PEN

CH8 Pin Enable

CH9PEN

CH9 Pin Enable

CH10PEN

CH10 Pin Enable

CH11PEN

CH11 Pin Enable

CH12PEN

CH12 Pin Enable

CH13PEN

CH13 Pin Enable

CH14PEN

CH14 Pin Enable

CH15PEN

CH15 Pin Enable

CH16PEN

CH16 Pin Enable

CH17PEN

CH17 Pin Enable

CH18PEN

CH18 Pin Enable

CH19PEN

CH19 Pin Enable

CH20PEN

CH20 Pin Enable

CH21PEN

CH21 Pin Enable

CH22PEN

CH22 Pin Enable

CH23PEN

CH23 Pin Enable

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